Gate arrays are uniform patterns of hundreds or thousands of unconnected transistor-level gate cells. Due to the availability to a designer of means to connect the cells via interlevel contacts and interlevel routing performed at a late stage in processing, many custom circuits may be created from a basic gate array. A basic design objective of gate arrays is to make the gate cells easily accessible to power and ground busses since the gate cells are typically placed on a level different from the power and ground busses. However, when hundreds or thousands of transistors are connected in an array, very large current spikes may develop in certain locations of the array when the transistors switch at the same time. When power busses are not routed closely to the transistors, noise may exist on internal nodes and create logic errors in the gate array cells. When current spikes exist at the inputs of the gate array, these spikes may also create logic errors in the internal portion of the gate array. Some gate arrays utilize separate digital and analog power and ground distribution busses to minimize analog circuit noise from digital circuitry as noted on page 166 of "CMOS Uncommitted Logic Arrays Are Part-Digital, Part-Analog", by Yoder, Electronics, Jan. 13, 1981. However, when such gate arrays have a large plurality of input/output cells per side of the array, large current spikes at the output may still generate noise errors in the internal digital circuitry.